module DAC_8811(
    input   sys_clk,
    input   rst_n,
    input   updatreg,
    input   [15:0] dac_data_in,
    
    output  reg dac_clk,
    output  reg dac_cs,
    output  reg dac_data_out,
    output  reg dac_con
    );
reg [6:0] cnt;

always@(posedge sys_clk or negedge rst_n)
begin
    if(!rst_n)
        cnt <= 7'd0;
    else if(  (updatreg == 1'b1 )|(cnt!=7'd0) )
        begin
            if(cnt == 7'd66)
                cnt <= 7'd0;
            else
                cnt <= cnt +1'b1;
        end
    else
        cnt <= 7'd0;
end

//线性序列机控制进程
always@(posedge sys_clk or negedge rst_n)
begin
    if(!rst_n)
        begin
            dac_clk <= 1'b1;
            dac_cs <= 1'b1;
            dac_data_out <=1'b0;
            dac_con <= 1'b0;
        end  
   else begin
        case(cnt)
            0:
                begin
                    dac_clk <= 1'b1;
                    dac_data_out <=1'b0;
                    dac_con <= 1'b0;
                end
            1:dac_cs <= 1'b0;
            2:  
                begin
                    dac_cs <= 1'b0;
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[15];  
                end
            4:  dac_clk <= 1'b1;
            6:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[14];
                end
            8:  dac_clk <= 1'b1;
            10:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[13];
                end
            12: dac_clk <= 1'b1;
            14:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[12];
                end
            16: dac_clk <= 1'b1;
            18:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[11];
                end
            20: dac_clk <= 1'b1;
            22:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[10];
                end
            24:dac_clk <= 1'b1;
            26:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[9];
                end
            28:dac_clk <= 1'b1;
            30:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[8];
                end
            32:dac_clk <= 1'b1;
            34:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[7];
                end
            36:dac_clk <= 1'b1;
            38:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[6];
                end
            40:dac_clk <= 1'b1;
            42:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[5];
                end
            44:dac_clk <= 1'b1;
            46:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[4];
                end
            48:dac_clk <= 1'b1;
            50:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[3];
                end
            52:dac_clk <= 1'b1;
            54:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[2];
                end
            56:dac_clk <= 1'b1;
            58:
                begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[1];
                end
            60:dac_clk <= 1'b1;
            62:begin
                    dac_clk <= 1'b0;
                    dac_data_out <= dac_data_in[0];
                end
            64:dac_clk <= 1'b1;
                
            66:
               begin
                    dac_cs <= 1'b1;
                    dac_data_out <=1'b0;
                    dac_con <=1'b1;
                end
            default:;
        endcase
        end
end

endmodule
